1. Field of the Invention
The present invention is related to a development system of a microprocessor for an application program including integer division or integer remainder operations, and more particularly, to a development system having a compiler, which is capable of greatly reducing the number of operating cycles required for integer division or an integer remainder operation of a microprocessor.
2. Description of the Related Art
For a microprocessor, division and remainder operations accompanying division among the four arithmetic operations require the most operating cycles. For example, in the case of a 32-bit unsigned operation, whereas addition and subtraction can be executed in one cycle, and multiplication can be executed in two cycles on an ordinary processor, division requires anywhere between 18-34 cycles.
The reason division is slow is because it cannot be achieved with a divider-oriented algorithm in a short operating cycle, and in most cases employs the same restoring method used for written calculations. The restoring method of a written calculation requires a number of machine cycles equivalent to the number of bits of the dividend.
FIG. 1 is a diagram showing an example of division using the restoring method. When 6-bit dividend “001110” is divided by 2-bit divisor “11,” division is completed by attempting to subtract the divisor “11” from the dividend, with “1” being assigned when subtraction is possible, and “0” being assigned when subtraction is not possible, and this operating cycle being repeated a number of times equivalent to the number of digits in the dividend. That is, a 6-bit dividend operation can be completed in a total of six cycles, the cycles S1-S6 in FIG. 1. With this method, when a dividend is 32 bits, division simply requires 32 cycles.
In another division example, there is a method, whereby the number of bits capable of being processed in one cycle can be increased to two bits or three bits instead of one bit. In this case, in order to process two bits at a time relative to the dividend, a determination is made as to whether or not divisor “11”×1, divisor “11”×2, and divisor “11”×3 can be subtracted from the dividend, and the respective answers are given as “01”, “10” and “11”. Therefore, the hardware constitution of the divider becomes more complex, and increased power consumption is incurred in line therewith.
As another division example, there is also a method, whereby division is performed via the above-mentioned restoring method by checking to determine the presence of “0” in the high bits of the dividend and beginning when “1” is initially detected. A read-zero method like this requires hardware that checks the high bits for “0”, and, in addition, gives rise to the problem that the execute cycle differs according to the dividend, making it difficult to manage a division operation schedule.
In an application program, it is well known that wasteful division is eliminated by creating a program code that replaces a division operation with the multiplication of a dividend by the reciprocal number of a divisor. Therefore, a compiler, which analyzes an application program and converts it to an assembly code (code corresponding to an object code), can be considered for replacing a division operation inside an application program with the multiplication of the dividend by the reciprocal of the divisor in accordance with this method.
However, since a compiler cannot know how a programer that describes an application program determines the significant digit of a division operation, this kind of replacement cannot be said to be very desirable.
In addition to the above, it is not really desirable to make the constitution of a divider more complex in line with increasing the frequency of a microprocessor. This is because the period of one cycle becomes shorter pursuant to increasing the frequency, making it difficult for a divider of a complex constitution to finish this operation within a cycle.